Ground bounce can occur with high-speed digital integrated circuits (“ICs”) when multiple outputs change states simultaneously. Ground bounce can cause several undesired effects, both on the output of the switching device and on the receiving logic device. In order to avoid problems associated with ground bounce, manufacturers of ICs publish tables of guidelines for the maximum number of simultaneous switching outputs (“SSOs”) that each power/ground pair (driver) of an IC can provide without violating a specified ground bounce limit.
Ground bounce is primarily due to current changes in the combined inductance from ground pins, bond wires, and ground metallization. The internal ground level of the IC deviates from the external system ground level for a short duration (typically a few nanoseconds) after multiple outputs change state simultaneously.
The switching output is supposed to provide a logical “1” or logical “0”. Ground bounce can affect whether the switching output is properly read by receiving logic because the logical state is typically derived by comparing an incoming signal to the internal ground of the switching device. Noise on the signal and/or ground can alter the logical state read by the receiving logic and cause erroneous operation of the system if the ground bounce amplitude exceeds the instantaneous noise margin. For example, ground bounce noise on a non-changing input that raises the internal ground level above the instantaneous noise margin might unintentionally toggle the logical state of a receiving logic input. In other words, the ground bounce can be interpreted as a switched signal on an input that isn't being switched.
The ground bounce limit is set according to the most sensitive input driven by the switching device. Given a ground bounce limit, the number of SSOs (“drivers”) allowed on a power/ground pair is set according to several assumptions. Manufacturers print tables of SSO guidelines for various types of logic, drivers, and packages. The SSO guidelines assume various values for parameters that affect ground bounce voltage.
Table 1, which is merely exemplary, is a table of the maximum number of SSOs per power/ground pair published by XILINX, INC. of San Jose, Calif. for using a VIRTEX™ FPGA in a digital switching system. The first column refers to the logic standard, such as whether the receiving logic is low-voltage complimentary metal-oxide-semiconductor, second generation (“LVCMOS2”) or low-voltage transistor—transistor logic (“LVTTL”), which can have a fast slew rate or a slow slew rate. The recommended maximum number of SSOs depends on many factors, such as how much current is drawn by the loads, the total input capacitance of the loads being driven, and the type of package the FPGA will be housed in, such as a ball grid array (“BGA”) package, a high-heat dissipation quad flat package (“HQ”), or a plastic quad flat package (“PQ”). For example, in the first row of Table 1 the number “10” relates to the “Package Type” “BGA” and indicates that no more than 10 LVCMOS2-type SSOs are recommended for the FPGA when it is in a BGA package. Similarly, the number “7” relates to the “Package Type” “HQ” and indicates that no more than 7 LVCMOS2-type SSOs are recommended for the FPGA when it is in a HQ package. And the number “5” relates to the “Package Type” “PQ” and indicates that no more than 7 LVCMOS2-type SSOs are recommended for the FPGA when it is in a PQ package.
TABLE 1Maximum Number of Recommended Simultaneous SwitchingOutputsReceiving Logic StandardPackage TypeBGAHQPQLVCMOS21075LVTTL, Fast Slew Rate, 8 mA drive13107LVTTL, Fast Slew Rate, 12 mA drive1075LVTTL, Fast Slew Rate, 24 mA drive543LVTTL, Slow Slew Rate, 8 mA drive221712LVTTL, Slow Slew Rate, 12 mA drive17129LVTTL, Slow Slew Rate, 24 mA drive975
Table 1 is a small subset of the type of SSO guideline tables typically published by a device manufacturer for use as an engineering design tool. Such tables often include many more types of receiving logic standards, package types, and loads. The drivers in the FPGA are configurable, and are selectively programmed to provide the proper drive characteristics for the intended receiving logic. Typical SSO guideline tables frequently include several hundred entries.
A design engineer using Table 1 would see that a power/ground pair of the FPGA could accommodate 13 8 mA LVTTL fast-slew loads when the FPGA is in a BGA package, or 22 8 mA LVTTL slow-slew loads. Fewer SSOs are recommended as the slew rate increases, and fewer SSOs are recommended as the driver current increases; however, these are merely general trends.
The SSO design tables are generated using circuit-simulation software. A circuit model of the switching device, receiving logic, package, and PWB is created. A simulator is used to iteratively determine how many SSOs may be driven before a specified noise voltage limit is exceeded. The parameters are varied one-by-one to obtain the table entries. The process of generating a complete SSO guideline table is long and tedious. To complicate matters, several values that affect the SSO guidelines are assumed during the simulation, such as the inductance of vias in a PWB, or of a trace in a package. Packing and PWBs continue to change, which changes the actual inductance from that which was assumed when generating the SSO guideline table. Similarly, the maximum allowable ground bounce voltage is not the same for all receiving logic, and new types of receiving logic may have a lower ground bounce voltage specification.
For example, LVTTL-type drivers can have as much as 800 mV of ground bounce noise before tripping an input-low threshold. Digital switching devices having an assumed ground bounce specification of ±600 mV when used with a PWB having an inductance to ground of 1 nH should work with the LVTTL driver if the SSO guidelines (which assumed a 1 nH board-level inductance) are followed. However, advances in PWB manufacturing have increased actual board-level inductance to 2–3 nH, and actual ground bounce voltage for the digital switching device might exceed the 800 mV threshold of the LVTTL-type driver when used on a newer PWB. Similarly, as the supply voltage level of logic devices decreases, components generally tolerate less ground bounce noise. Some new receiving logic devices tolerate as little as 400 mV undershoot at the input, and might not operate correctly if a SSO guideline table assuming a maximum of ±600 mV was used to design the interface between the switching device (e.g. FPGA) and the receiving logic.
It is desirable to provide guidance for managing ground bounce at the package level for a digital switching device without having to re-establish and re-publish SSO guideline tables. It is further desirable to provide flexibility in determining the maximum number of SSOs to account for different types of output drivers on a single I/O bank of a digital switching device. It is also desirable to be able to analyze ground bounce voltage for an entire digital switching device.